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Communication Dans Un Congrès Année : 2013

FPGA Implementation of a Parameterized Fourier Synthesizer

Rui Yang
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J.G. Wang
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Benoit Clement
Ali Mansour


Field-Programmable Gate Array (FPGA) offers advantages for many applications, particularly where missions are complex and time performance is critical. For small-production digital acoustic synthesizers, FPGA can achieve the above-mentioned tighter system requirements with low total system costs on single chip. In this manuscript, a real-time acoustic synthesizer is implemented using Fourier series algorithm on Altera's Cyclone II FPGA chip. This work emphasizes systematic designs and parallel computations. The proposed system includes a flexible processor and a parallel parameterized acoustic module. On one hand, the Nios II embedded processor, which is relatively low-speed component, is used to generate commands and configure high-speed acoustic module parameters. On the other hand, acoustic module which should require high-speed components contains 4 parallel architectures to gain high-speed simultaneous calculus of 4 independent digital timbres. Every timbre is equivalent to 16 parallel high-precision harmonic channels with 0.3 % frequency error. Experimental results corroborate the fact that a single FPGA chip can achieve complex missions and attain real-time performances.
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Dates et versions

hal-00917013 , version 1 (11-12-2013)


  • HAL Id : hal-00917013 , version 1


Rui Yang, J.G. Wang, Benoit Clement, Ali Mansour. FPGA Implementation of a Parameterized Fourier Synthesizer. IEEE International Conference on Electronics, Circuits, and Systems, Dec 2013, Abu Dhabi, United Arab Emirates. ⟨hal-00917013⟩
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