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Communication Dans Un Congrès Année : 2020

Menhir: Generic High-Speed FPGA Model-Checker

Ciprian Teodorov
Loïc Lagadec


Among formal methods, model-checking offers a high-level of automation and can lower the cost of the verification process. Two preliminary studies on FPGA model-checking show a high-performance increase, thanks to the massive parallelism and precise memory control opportunities. However, these approaches rely on HDL-based ad-hoc model encoding, and miss the importance of decoupling the modeling language from the verification core, which greatly limits their usability. In this paper we propose Menhir, a new highly modular hardware model-checker, inspired by the architecture of software verification frameworks. Menhir is based on a generic language-verification interface which isolates the modeling-language semantics from the verification core, allowing their independent evolution. Menhir opens the architecture to the whole spectrum of modeling languages. Moreover, it proposes a polymorphic verification core, which offers a continuum between partial and exhaustive verification, with promising performances.
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Dates et versions

hal-03028409 , version 1 (27-11-2020)



Émilien Fournier, Ciprian Teodorov, Loïc Lagadec. Menhir: Generic High-Speed FPGA Model-Checker. 2020 23rd Euromicro Conference on Digital System Design (DSD), Aug 2020, Kranj, Slovenia. pp.65-72, ⟨10.1109/DSD51259.2020.00022⟩. ⟨hal-03028409⟩
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