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Towards a Hardware DSL Ecosystem: RubyRTL and FriendsOSDA'2020 Open Source Hardware Design, colocated with DATE'20, Mar 2020, Grenoble, France
Communication dans un congrès
hal-02513256v1
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Detection of AIS messages falsifications and spoofing by checking messages compliance with TDMA protocolDigital Signal Processing, 2023, 136, pp.103983. ⟨10.1016/j.dsp.2023.103983⟩
Article dans une revue
hal-04077623v1
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Using MARTE in the MOPCOM SoC/SoPC MethodologyWorkshop MARTE, Colocated with DATE, Mar 2008, Munich, Germany
Communication dans un congrès
hal-00517468v1
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Overlay Architectures For FPGA Resource VirtualizationGDR SOC SIP, Jun 2016, Nantes, France
Communication dans un congrès
hal-01405912v1
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Early exploring design alternatives of smart sensor software with Model of Computation implemented with actorsESUG 2013 - 21th International Smalltalk Conference, Sep 2013, Annecy, France
Communication dans un congrès
hal-00913335v1
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CDFG Platform in MORPHEUSAETHER - MORPHEUS Workshop AMWAS'07, Oct 2007, Paris, France
Communication dans un congrès
hal-00487063v1
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Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level SynthesisDATE'21 Design Automation and Test in Europe, Feb 2021, Grenoble (virtuel), France
Communication dans un congrès
hal-03228922v1
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Model-Driven Toolset for Embedded Reconfigurable Cores: Flexible Prototyping and Software-like DebuggingScience of Computer Programming, 2014, pp.1. ⟨10.1016/j.scico.2014.02.015⟩
Article dans une revue
hal-00998533v1
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Communication-aware Parallelization Strategies for High Performance Applications.ISVLSI'15 - IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France
Communication dans un congrès
hal-01174435v1
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An Integrated Toolchain for Overlay-centric System-on-chip13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip 2018 (ReCoSoC 2018), Jul 2018, Lille, France. ⟨10.1109/ReCoSoC.2018.8449388⟩
Communication dans un congrès
hal-01867638v1
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Modélisation algorithmique et synthèse d'architectures assistées par model-checkingCAL 2012-, May 2012, Montpellier, France
Communication dans un congrès
hal-00703785v1
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A High-Level Programming Model to Ease Pipeline Parallelism Expression On Shared Memory Multicore ArchitecturesHPC 2014, Apr 2014, Tampa, FL, United States. pp.XX
Communication dans un congrès
hal-00989661v1
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MHPM : Multi-Scale Hybrid Programming Model A flexible parallelization MedthodologyHPCC 2012, Jun 2012, Liverpool, United Kingdom
Communication dans un congrès
hal-00728364v1
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Overlay Architectures for Heterogeneous FPGA Cluster Management.DASIP 2016, Oct 2016, Rennes, France
Communication dans un congrès
hal-01405890v1
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A Prototyping Platform for Virtual Reconfigurable UnitsRECOSOC 2014, May 2014, Montpellier, France
Communication dans un congrès
hal-01006128v1
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JOG : une approche haut niveau des systèmes embarqués via Armadeus et Java3èmes Journées Démonstrateurs 2010, Nov 2010, Angers, France
Communication dans un congrès
hal-00911269v1
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HLS-based Accelerated Simulation of Large Scale Cyber-Physical Systems on FPGAsIEEE International NEWCAS Conference, Jul 2022, Montreal, Canada. ⟨10.1109/NEWCAS52662.2022.9842250⟩
Communication dans un congrès
hal-03839510v1
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Procédé de configuration d'un circuit logique programmable, circuit logique programmable et dispositif pour implémenter le procédéFrance, N° de brevet: FR3115134. 2022
Brevet
hal-04032489v1
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MoPCoM Methodology: Focus on Models of Computation6th European Conference on Modelling Foundations and Applications (ECMFA'10), Jun 2010, Paris, France. pp.Non renseigne
Communication dans un congrès
hal-00517464v1
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Tackling Real-Time Signal Processing Applications on Shared Memory Multicore Architectures Using XPUERTS 2014, Feb 2014, Toulouse, France
Communication dans un congrès
hal-00958087v1
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XPU: A C++ Metaprogramming Approach to Ease Parallelism Expression: Parallelization Methodology, Internal Design and Practical ApplicationParallel Programming: Practical Aspects, Models and Current Limitations, NOVA publishers, pp.175-198, 2014, 978-1-60741-263-2
Chapitre d'ouvrage
hal-01090466v1
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Stratégie de détection des Falsifications des Positions des Messages AIS Basée sur l'Application du Filtre IMMGretsi'22 XXVIIIème Colloque Francophone de Traitement du Signal et des Images, Sep 2022, Nancy, France
Communication dans un congrès
hal-03859377v1
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From system-level models to heterogeneous embedded systemsRITF 2012 - Recherche et Innovation pour les Transports du Futur, Nov 2012, Paris, France. pp.XX
Communication dans un congrès
hal-00771758v1
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AN EXPERIMENTAL TOOLCHAIN BASED ON HIGH-LEVEL DATAFLOW MODELS OF COMPUTATION FOR HETEROGENEOUS MPSOCDASIP, Oct 2012, Karlsruhe, Germany
Communication dans un congrès
hal-00749175v1
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Soft timing closure for soft programmable logic cores: The ARGen approachARC 2017 - 13th International Symposium on Applied Reconfigurable Computing, Delft University of Technology Apr 2017, Delft, Netherlands
Communication dans un congrès
hal-01475251v1
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ZeFF : Une plateforme pour l’intégration d’architectures overlay dans le CloudCOMPAS 2016, Jul 2016, Lorient, France
Communication dans un congrès
hal-01405860v1
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Protecting Behavioral IPs During Design Time: Key-Based Obfuscation Techniques for HLS in the CloudBehavioral Synthesis for Hardware Security, Springer International Publishing; Springer International Publishing, pp.71-93, 2022, ⟨10.1007/978-3-030-78841-4_5⟩
Chapitre d'ouvrage
hal-04115023v1
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DESIGN AND IMPLEMENTATION OF A CACHE HIERARCHY-AWARE TASK SCHEDULING FOR PARALLEL LOOPS ON MULTICORE ARCHITECTURESPDCTA 2014, Feb 2014, Sydney, Australia
Communication dans un congrès
hal-00958096v1
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UML/MARTE Process for SoC/SoPCEmbedded Real Time Software and Systems Symposium, 2010, Toulouse, France. pp.201,209
Communication dans un congrès
hal-00730497v1
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Using MARTE in a Co-Design MethodologyMARTE UML profile workshop co-located with DATE'08, Mar 2008, Munich, Germany. 6 p
Communication dans un congrès
hal-00354356v1
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